1. Field of the Invention
The present invention relates to a thin film transistor (TFT) and a flat panel display having the same and, more particularly, to a bottom gate TFT and a flat panel display having the same.
2. Description of the Related Technology
In general, a thin film transistor (TFT) includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor layer includes source and drain regions, and a channel region interposed therebetween. The semiconductor layer may be made of polysilicon or amorphous silicon. Because the polysilicon is higher in electron mobility than the amorphous silicon, the polysilicon is usually used as the semiconductor layer.
The polysilicon TFT is classified into a top gate type that a gate electrode is disposed above a channel region and a bottom gate type that a gate electrode is disposed below a channel region. The bottom gate polysilicon TFT has an advantage in that a low temperature process may be performed compared to the top gate polysilicon TFT.
Korean Patent Registration No. 10-0317640 discloses a bottom gate polysilicon TFT and is incorporated herein by reference.
FIGS. 1A and 1B are cross-sectional views illustrating a method of fabricating the TFT disclosed in Korean Patent Registration No. 10-0317640, and FIG. 1C is a plan view corresponding to FIG. 1A.
Referring to FIG. 1A, a gate electrode 15 is formed on a substrate 10, and an insulating layer 20 and a pure amorphous silicon layer 25 are sequentially formed over the gate electrode 15 and the substrate 10. An etch stop layer 30 is formed on the pure amorphous silicon layer 25, and then the pure amorphous silicon layer 25 is metal-treated. When the etch stop layer 30 is formed in the shape of an island disposed in the same direction as the gate electrode 15, the entire pure amorphous silicon layer 25 surrounding the etch stop layer 30 may be metal-treated (see FIG. 1C). The metal-treated pure amorphous silicon layer 25 is subjected to an ion doping process using the etch stop layer 30 as a doping barrier layer.
Following the ion doping process, a direct high voltage is applied to a surface of the ion-doped pure amorphous silicon layer 25 to crystallize the ion-doped pure amorphous silicon layer 25. The pure amorphous silicon layer 25 below the etch stop layer 30 may be crystallized laterally without directly contacting a metal. However, because the pure amorphous silicon layer 25 surrounding the etch stop layer 30 is metal-treated, the crystallized silicon layer below the etch stop layer 30 may be contaminated due to metal introduced from a peripheral region of the etch stop layer 30.
Referring to FIG. 1B, the crystallized polysilicon layer is patterned in the shape of an island to form an active layer 25′. Subsequently, a source electrode 40 and a drain electrode 42 are formed over the active layer 25′ and the insulating layer 20, thereby completing the TFT. In the TFT, the active layer 25′ below the etch stop layer 30 serves as a channel region. As described above, however, the channel region may be contaminated by metal from the metal treatment, thereby leading to a relatively high leakage current. This high leakage current may also negatively effect the performance of an organic light emitting diode coupled to the transistor in a pixel circuit, thereby negatively effecting the performance of a flat panel display incorporating such a pixel circuit.